Specman Verification
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Randomize a variable in a module 
Friday, February 6, 2009, 06:43 AM - The verification hood
Or better put, to randomize a variable with constraints anywhere you want, use std::randomize() as shown below:

module x();
   int y;

   initial begin
      std::randomize(y) with {y<5; y>2;};
      $display(y);
   end
endmodule
      




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Check a SystemVerilog vector for X or Z values 
Thursday, January 29, 2009, 01:11 AM - The verification hood
module x();
   logic[3:0] a = 4'b0x10;
   logic[3:0] b = 4'bz011;
   
   initial begin
      if (^a === 'x) $display("a contains x or z");
      if (^b === 'x) $display("b contains x or z");

      // note that only xor always works, but not "or" or "and"
      if (|a === 'x) $display("this will not detect the x");
   end
endmodule


See also here
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Square root in SystemVerilog 
Wednesday, January 28, 2009, 10:21 PM - The verification hood
module x();
   real t=10.0;

   initial 
      // either...
     t = t**0.5; 
      // or... 
     t = $sqrt(t);       
endmodule


The first option, which doesn't use a system function call, is probably slightly more efficient...

see other arithmatic functions here


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