Tips for HVL and HDL users with special emphasis on Specman-e, SystemVerilog and Questa

Specman Verification

Tips for HVL and HDL users with special emphasis on Specman-e, SystemVerilog and Questa

Verification engineer? Verifigen has the right project for you!

Links
Home
Contact Me/Contract Me
CV and picture

The essentials
Specman Tutorial
(Evolving) SV Tutorial
Specman And SystemVerilog
Work Interview Questions

verification links
Coolverification
Deep chip
Digital verification
Harry...the ASIC guy
Think verification
Verification guild
Verilab's blog
VLSI home page
Cadence's Specman blog
FPGA simulation
Pini's verification site
Intelligentdv

Verification goodies
e plug in for Eclipse
Soft constraints in SV
Verilab's e toolkit

Personal
verisense
captain-book

Archives

«	December 2006					»
Sun	Mon	Tue	Wed	Thu	Fri	Sat
					1	2
3	4	5	6	7	8	9
10	11	12	13	14	15	16
17	18	19	20	21	22	23
24	25	26	27	28	29	30
31
06/19/13

Categories
Hardcore verification
The verification hood
Computer stuff
Personal

Search:

Most Recent Entries

SystemVerilog source bank

Me @ DVCon

Add color to your UVM environment

DeepChip in the HolyLand!!! - 1st November at Hilton TA

Specman profiler for beginners

Greping all loaded e files for a regex

Powered by Simple PHP Blog 0.4.6.1

Get RSS 2.0 Feed

Powered by PHP 4.3.11

Get Atom 0.3 Feed

Powered by Plain text files

Get RDF 1.0 Feed

Add to Technorati Favorites