Class Index
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P
 Phasing Implementation
U
 uvm_*_export#(REQ,RSP)
 uvm_*_export#(T)
 uvm_*_imp#(REQ,RSP,IMP,REQ_IMP,RSP_IMP)
 uvm_*_imp#(T,IMP)
 uvm_*_port#(REQ,RSP)
 uvm_*_port#(T)
 uvm_agent
 uvm_algorithmic_comparator#(BEFORE,AFTER,TRANSFORMER)
 uvm_analysis_export
 uvm_analysis_imp
 uvm_analysis_port
 uvm_barrier
 uvm_bottomup_phase
 uvm_build_phase
 uvm_built_in_clone#(T)
 uvm_built_in_comp#(T)
 uvm_built_in_converter#(T)
 uvm_built_in_pair#(T1,T2)
 uvm_callback
 uvm_callback_iter
 uvm_callbacks#(T,CB)
 uvm_callbacks_objection
 uvm_check_phase
 uvm_class_clone#(T)
 uvm_class_comp#(T)
 uvm_class_converter#(T)
 uvm_class_pair#(T1,T2)
 uvm_cmdline_processor
 uvm_comparer
 uvm_component
 uvm_component_registry#(T,Tname)
 uvm_config_db
 uvm_config_db_options
 uvm_configure_phase
 uvm_connect_phase
 uvm_domain
 uvm_driver#(REQ,RSP)
 uvm_end_of_elaboration_phase
 uvm_env
 uvm_event
 uvm_event_callback
 uvm_extract_phase
 uvm_factory
 uvm_final_phase
 uvm_hdl_path_concat
 uvm_heartbeat
 uvm_in_order_built_in_comparator#(T)
 uvm_in_order_class_comparator#(T)
 uvm_in_order_comparator#(T,comp_type,convert,pair_type)
 uvm_line_printer
 uvm_main_phase
 uvm_mem
 uvm_mem_access_seq
 uvm_mem_mam
 uvm_mem_mam_cfg
 uvm_mem_mam_policy
 uvm_mem_region
 uvm_mem_shared_access_seq
 uvm_mem_single_access_seq
 uvm_mem_single_walk_seq
 uvm_mem_walk_seq
 uvm_monitor
 uvm_object
 uvm_object_registry#(T,Tname)
 uvm_object_string_pool#(T)
 uvm_object_wrapper
 uvm_objection
 uvm_objection_callback
 uvm_packer
 uvm_phase
 uvm_pool#(KEY,T)
 uvm_port_base#(IF)
 uvm_port_component#(PORT)
 uvm_port_component_base
 uvm_post_configure_phase
 uvm_post_main_phase
 uvm_post_reset_phase
 uvm_post_shutdown_phase
 uvm_pre_configure_phase
 uvm_pre_main_phase
 uvm_pre_reset_phase
 uvm_pre_shutdown_phase
 uvm_printer
 uvm_printer_knobs
 uvm_push_driver#(REQ,RSP)
 uvm_push_sequencer#(REQ,RSP)
 uvm_queue#(T)
 uvm_random_stimulus#(T)
 uvm_recorder
 uvm_reg
 uvm_reg_access_seq
 uvm_reg_adapter
 uvm_reg_backdoor
 uvm_reg_bit_bash_seq
 uvm_reg_block
 uvm_reg_bus_op
 uvm_reg_cbs
 uvm_reg_field
 uvm_reg_fifo
 uvm_reg_file
 uvm_reg_frontdoor
 uvm_reg_hw_reset_seq
 uvm_reg_indirect_data
 uvm_reg_item
 uvm_reg_map
 uvm_reg_mem_access_seq
 uvm_reg_mem_built_in_seq
 uvm_reg_mem_hdl_paths_seq
 uvm_reg_mem_shared_access_seq
 uvm_reg_predictor
 uvm_reg_read_only_cbs
 uvm_reg_sequence
 uvm_reg_shared_access_seq
 uvm_reg_single_access_seq
 uvm_reg_single_bit_bash_seq
 uvm_reg_tlm_adapter
 uvm_reg_write_only_cbs
 uvm_report_catcher
 uvm_report_handler
 uvm_report_object
 uvm_report_phase
 uvm_report_server
 uvm_reset_phase
 uvm_resource#(T)
 uvm_resource_base
 uvm_resource_db
 uvm_resource_db_options
 uvm_resource_options
 uvm_resource_pool
 uvm_resource_types
 uvm_root
 uvm_run_phase
 uvm_scoreboard
 uvm_seq_item_pull_export#(REQ,RSP)
 uvm_seq_item_pull_imp#(REQ,RSP,IMP)
 uvm_seq_item_pull_port#(REQ,RSP)
 uvm_sequence#(REQ,RSP)
 uvm_sequence_base
 uvm_sequence_item
 uvm_sequencer#(REQ,RSP)
 uvm_sequencer_base
 uvm_sequencer_param_base#(REQ,RSP)
 uvm_shutdown_phase
 uvm_sqr_if_base#(REQ,RSP)
 uvm_start_of_simulation_phase
 uvm_subscriber
 uvm_table_printer
 uvm_task_phase
 uvm_test
 uvm_tlm_analysis_fifo
 uvm_tlm_b_initiator_socket
 uvm_tlm_b_initiator_socket_base
 uvm_tlm_b_passthrough_initiator_socket
 uvm_tlm_b_passthrough_initiator_socket_base
 uvm_tlm_b_passthrough_target_socket
 uvm_tlm_b_passthrough_target_socket_base
 uvm_tlm_b_target_socket
 uvm_tlm_b_target_socket_base
 uvm_tlm_b_transport_export
 uvm_tlm_b_transport_imp
 uvm_tlm_b_transport_port
 uvm_tlm_extension
 uvm_tlm_extension_base
 uvm_tlm_fifo
 uvm_tlm_fifo_base#(T)
 uvm_tlm_generic_payload
 uvm_tlm_gp
 uvm_tlm_if
 uvm_tlm_if_base#(T1,T2)
 uvm_tlm_nb_initiator_socket
 uvm_tlm_nb_initiator_socket_base
 uvm_tlm_nb_passthrough_initiator_socket
 uvm_tlm_nb_passthrough_initiator_socket_base
 uvm_tlm_nb_passthrough_target_socket
 uvm_tlm_nb_passthrough_target_socket_base
 uvm_tlm_nb_target_socket
 uvm_tlm_nb_target_socket_base
 uvm_tlm_nb_transport_bw_export
 uvm_tlm_nb_transport_bw_imp
 uvm_tlm_nb_transport_bw_port
 uvm_tlm_nb_transport_fw_export
 uvm_tlm_nb_transport_fw_imp
 uvm_tlm_nb_transport_fw_port
 uvm_tlm_req_rsp_channel#(REQ,RSP)
 uvm_tlm_time
 uvm_tlm_transport_channel#(REQ,RSP)
 uvm_topdown_phase
 uvm_transaction
 uvm_tree_printer
 uvm_utils
 uvm_vreg
 uvm_vreg_cbs
 uvm_vreg_field
 uvm_vreg_field_cbs
The API described here provides a general purpose testbench phasing solution, consisting of a phaser machine, traversing a master schedule graph, which is built by the integrator from one or more instances of template schedules provided by UVM or by 3rd-party VIP, and which supports implicit or explicit synchronization, runtime control of threads and jumps.
The bidirectional uvm_*_export is a port that forwards or promotes an interface implementation from a child component to its parent.
The unidirectional uvm_*_export is a port that forwards or promotes an interface implementation from a child component to its parent.
Bidirectional implementation (imp) port classes--An imp port provides access to an implementation of the associated interface to all connected ports and exports.
Unidirectional implementation (imp) port classes--An imp port provides access to an implementation of the associated interface to all connected ports and exports.
These bidirectional ports are instantiated by components that require, or use, the associated interface to convey transactions.
These unidirectional ports are instantiated by components that require, or use, the associated interface to convey transactions.
virtual class uvm_agent extends uvm_component
The uvm_agent virtual class should be used as the base class for the user- defined agents.
class uvm_algorithmic_comparator #( type  BEFORE  =  int,
type  AFTER  =  int,
type  TRANSFORMER  =  int ) extends uvm_component
Compares two streams of data objects of different types, BEFORE and AFTER.
class uvm_analysis_export #(
    type  T  =  int
) extends uvm_port_base #(uvm_tlm_if_base #(T,T))
Exports a lower-level uvm_analysis_imp to its parent.
class uvm_analysis_imp #(
    type  T  =  int,
    type  IMP  =  int
) extends uvm_port_base #(uvm_tlm_if_base #(T,T))
Receives all transactions broadcasted by a uvm_analysis_port.
class uvm_analysis_port # (
    type  T  =  int
) extends uvm_port_base # (uvm_tlm_if_base #(T,T))
Broadcasts a value to all subscribers implementing a uvm_analysis_imp.
class uvm_barrier extends uvm_object
The uvm_barrier class provides a multiprocess synchronization mechanism.
virtual class uvm_bottomup_phase extends uvm_phase
Virtual base class for function phases that operate bottom-up.
class uvm_build_phase extends uvm_topdown_phase
Create and configure of testbench structure
class uvm_built_in_clone #( type  T  =  int )
This policy class is used to clone built-in types via the = operator.
class uvm_built_in_comp #( type  T  =  int )
This policy class is used to compare built-in types.
class uvm_built_in_converter #( type  T  =  int )
This policy class is used to convert built-in types to strings.
class uvm_built_in_pair #( type  T1  =  int,
  T2  =  T1 ) extends uvm_object
Container holding two variables of built-in types (int, string, etc.)
class uvm_callback extends uvm_object
The uvm_callback class is the base class for user-defined callback classes.
class uvm_callback_iter#( type  T  =  uvm_object,
type  CB  =  uvm_callback )
The uvm_callback_iter class is an iterator class for iterating over callback queues of a specific callback type.
class uvm_callbacks #( type  T  =  uvm_object,
type  CB  =  uvm_callback ) extends uvm_typed_callbacks#(T)
The uvm_callbacks class provides a base class for implementing callbacks, which are typically used to modify or augment component behavior without changing the component class.
class uvm_callbacks_objection extends uvm_objection
The uvm_callbacks_objection is a specialized uvm_objection which contains callbacks for the raised and dropped events.
class uvm_check_phase extends uvm_bottomup_phase
Check for any unexpected conditions in the verification environment.
class uvm_class_clone #( type  T  =  int )
This policy class is used to clone class objects.
class uvm_class_comp #( type  T  =  int )
This policy class is used to compare two objects of the same type.
class uvm_class_converter #( type  T  =  int )
This policy class is used to convert a class object to a string.
class uvm_class_pair #( type  T1  =  int,
  T2  =  T1 ) extends uvm_object
Container holding handles to two objects whose types are specified by the type parameters, T1 and T2.
class uvm_cmdline_processor extends uvm_report_object
This class provides an interface to the command line arguments that were provided for the given simulation.
class uvm_comparer
The uvm_comparer class provides a policy object for doing comparisons.
virtual class uvm_component extends uvm_report_object
The uvm_component class is the root base class for UVM components.
class uvm_component_registry #(
    type  T  =  uvm_component,
    string  Tname  =  "<unknown>"
) extends uvm_object_wrapper
The uvm_component_registry serves as a lightweight proxy for a component of type T and type name Tname, a string.
class uvm_config_db#( type  T  =  int ) extends uvm_resource_db#(T)
All of the functions in uvm_config_db#(T) are static, so they must be called using the :: operator.
Provides a namespace for managing options for the configuration DB facility.
class uvm_configure_phase extends uvm_task_phase
The SW configures the DUT.
class uvm_connect_phase extends uvm_bottomup_phase
Establish cross-component connections.
class uvm_domain extends uvm_phase
Phasing schedule node representing an independent branch of the schedule.
class uvm_driver #( type  REQ  =  uvm_sequence_item,
type  RSP  =  REQ ) extends uvm_component
The base class for drivers that initiate requests for new transactions via a uvm_seq_item_pull_port.
class uvm_end_of_elaboration_phase extends uvm_bottomup_phase
Fine-tune the testbench.
virtual class uvm_env extends uvm_component
The base class for hierarchical containers of other components that together comprise a complete environment.
class uvm_event extends uvm_object
The uvm_event class is a wrapper class around the SystemVerilog event construct.
virtual class uvm_event_callback extends uvm_object
The uvm_event_callback class is an abstract class that is used to create callback objects which may be attached to uvm_events.
class uvm_extract_phase extends uvm_bottomup_phase
Extract data from different points of the verficiation environment.
class uvm_factory
As the name implies, uvm_factory is used to manufacture (create) UVM objects and components.
class uvm_final_phase extends uvm_topdown_phase
Tie up loose ends.
class uvm_hdl_path_concat
Concatenation of HDL variables
Heartbeats provide a way for environments to easily ensure that their descendants are alive.
class uvm_in_order_built_in_comparator #(
    type  T  =  int
) extends uvm_in_order_comparator #(T)
This class uses the uvm_built_in_* comparison, converter, and pair classes.
class uvm_in_order_class_comparator #(
    type  T  =  int
) extends uvm_in_order_comparator #( T , uvm_class_comp #( T ) , uvm_class_converter #( T ) , uvm_class_pair #( T, T ) )
This class uses the uvm_class_* comparison, converter, and pair classes.
Compares two streams of data objects of the type parameter, T.
class uvm_line_printer extends uvm_tree_printer
The line printer prints output in a line format.
class uvm_main_phase extends uvm_task_phase
Primary test stimulus.
class uvm_mem extends uvm_object
Memory abstraction base class
class uvm_mem_access_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Verify the accessibility of all memories in a block by executing the uvm_mem_single_access_seq sequence on every memory within it.
class uvm_mem_mam
Memory allocation manager
class uvm_mem_mam_cfg
Specifies the memory managed by an instance of a uvm_mem_mam memory allocation manager class.
class uvm_mem_mam_policy
An instance of this class is randomized to determine the starting offset of a randomly allocated memory region.
class uvm_mem_region
Allocated memory region descriptor
class uvm_mem_shared_access_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Verify the accessibility of a shared memory by writing through each address map then reading it via every other address maps in which the memory is readable and the backdoor, making sure that the resulting value matches the written value.
class uvm_mem_single_access_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Verify the accessibility of a memory by writing through its default address map then reading it via the backdoor, then reversing the process, making sure that the resulting value matches the written value.
class uvm_mem_single_walk_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Runs the walking-ones algorithm on the memory given by the mem property, which must be assigned prior to starting this sequence.
class uvm_mem_walk_seq extends uvm_reg_sequence #( uvm_sequence  #(uvm_reg_item) )
Verifies the all memories in a block by executing the uvm_mem_single_walk_seq sequence on every memory within it.
virtual class uvm_monitor extends uvm_component
This class should be used as the base class for user-defined monitors.
virtual class uvm_object extends uvm_void
The uvm_object class is the base class for all UVM data and hierarchical classes.
class uvm_object_registry #(
    type  T  =  uvm_object,
    string  Tname  =  "<unknown>"
) extends uvm_object_wrapper
The uvm_object_registry serves as a lightweight proxy for an uvm_object of type T and type name Tname, a string.
class uvm_object_string_pool #( type  T  =  uvm_object ) extends uvm_pool #(string,T)
This provides a specialization of the generic uvm_pool #(KEY,T) class for an associative array of uvm_object-based objects indexed by string.
virtual class uvm_object_wrapper
The uvm_object_wrapper provides an abstract interface for creating object and component proxies.
class uvm_objection extends uvm_report_object
Objections provide a facility for coordinating status information between two or more participating components, objects, and even module-based IP.
class uvm_objection_callback extends uvm_callback
The uvm_objection is the callback type that defines the callback implementations for an objection callback.
The uvm_packer class provides a policy object for packing and unpacking uvm_objects.
class uvm_phase extends uvm_object
This base class defines everything about a phase: behavior, state, and context.
class uvm_pool #( type  KEY  =  int,
  T  =  uvm_void ) extends uvm_object
Implements a class-based dynamic associative array.
virtual class uvm_port_base #( type  IF  =  uvm_void ) extends IF
Transaction-level communication between components is handled via its ports, exports, and imps, all of which derive from this class.
class uvm_port_component #(
    type  PORT  =  uvm_object
) extends uvm_port_component_base
See description of uvm_port_component_base for information about this class
virtual class uvm_port_component_base extends uvm_component
This class defines an interface for obtaining a port’s connectivity lists after or during the end_of_elaboration phase.
class uvm_post_configure_phase extends uvm_task_phase
After the SW has configured the DUT.
class uvm_post_main_phase extends uvm_task_phase
After enough of the primary test stimulus.
class uvm_post_reset_phase extends uvm_task_phase
After reset is de-asserted.
class uvm_post_shutdown_phase extends uvm_task_phase
After things have settled down.
class uvm_pre_configure_phase extends uvm_task_phase
Before the DUT is configured by the SW.
class uvm_pre_main_phase extends uvm_task_phase
Before the primary test stimulus starts.
class uvm_pre_reset_phase extends uvm_task_phase
Before reset is asserted.
class uvm_pre_shutdown_phase extends uvm_task_phase
Before things settle down.
virtual class uvm_printer
The uvm_printer class provides an interface for printing uvm_objects in various formats.
class uvm_printer_knobs
The uvm_printer_knobs class defines the printer settings available to all printer subtypes.
class uvm_push_driver #( type  REQ  =  uvm_sequence_item,
type  RSP  =  REQ ) extends uvm_component
Base class for a driver that passively receives transactions, i.e.
class uvm_push_sequencer #(
    type  REQ  =  uvm_sequence_item,
      RSP  =  REQ
) extends uvm_sequencer_param_base #(REQ, RSP)
class uvm_queue #( type  T  =  int ) extends uvm_object
Implements a class-based dynamic queue.
class uvm_random_stimulus #( type  T  =  uvm_transaction ) extends uvm_component
A general purpose unidirectional random stimulus class.
class uvm_recorder extends uvm_object
The uvm_recorder class provides a policy object for recording uvm_objects.
virtual class uvm_reg extends uvm_object
Register abstraction base class
class uvm_reg_access_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Verify the accessibility of all registers in a block by executing the uvm_reg_single_access_seq sequence on every register within it.
virtual class uvm_reg_adapter extends uvm_object
This class defines an interface for converting between uvm_reg_bus_op and a specific bus transaction.
class uvm_reg_backdoor extends uvm_object
Base class for user-defined back-door register and memory access.
class uvm_reg_bit_bash_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Verify the implementation of all registers in a block by executing the uvm_reg_single_bit_bash_seq sequence on it.
virtual class uvm_reg_block extends uvm_object
Block abstraction base class
Struct that defines a generic bus transaction for register and memory accesses, having kind (read or write), address, data, and byte enable information.
virtual class uvm_reg_cbs extends uvm_callback
Facade class for field, register, memory and backdoor access callback methods.
class uvm_reg_field extends uvm_object
Field abstraction class
class uvm_reg_fifo extends uvm_reg
This special register models a DUT FIFO accessed via write/read, where writes push to the FIFO and reads pop from it.
virtual class uvm_reg_file extends uvm_object
Register file abstraction base class
virtual class uvm_reg_frontdoor extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_sequence_item)
)
Facade class for register and memory frontdoor access.
class uvm_reg_hw_reset_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Test the hard reset values of registers
class uvm_reg_indirect_data extends uvm_reg
Indirect data access abstraction class
class uvm_reg_item extends uvm_sequence_item
Defines an abstract register transaction item.
class uvm_reg_map extends uvm_object
class uvm_reg_mem_access_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Verify the accessibility of all registers and memories in a block by executing the uvm_reg_access_seq and uvm_mem_access_seq sequence respectively on every register and memory within it.
class uvm_reg_mem_built_in_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Sequence that executes a user-defined selection of pre-defined register and memory test sequences.
class uvm_reg_mem_hdl_paths_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Verify the correctness of HDL paths specified for registers and memories.
class uvm_reg_mem_shared_access_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Verify the accessibility of all shared registers and memories in a block by executing the uvm_reg_shared_access_seq and uvm_mem_shared_access_seq sequence respectively on every register and memory within it.
class uvm_reg_predictor #( type  BUSTYPE  =  int ) extends uvm_component
Updates the register model mirror based on observed bus transactions
class uvm_reg_read_only_cbs extends uvm_reg_cbs
Pre-defined register callback method for read-only registers that will issue an error if a write() operation is attempted.
class uvm_reg_sequence #( type  BASE  =  uvm_sequence #(uvm_reg_item) ) extends BASE
This class provides base functionality for both user-defined RegModel test sequences and “register translation sequences”.
class uvm_reg_shared_access_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Verify the accessibility of a shared register by writing through each address map then reading it via every other address maps in which the register is readable and the backdoor, making sure that the resulting value matches the mirrored value.
class uvm_reg_single_access_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Verify the accessibility of a register by writing through its default address map then reading it via the backdoor, then reversing the process, making sure that the resulting value matches the mirrored value.
class uvm_reg_single_bit_bash_seq extends uvm_reg_sequence #(
    uvm_sequence  #(uvm_reg_item)
)
Verify the implementation of a single register by attempting to write 1’s and 0’s to every bit in it, via every address map in which the register is mapped, making sure that the resulting value matches the mirrored value.
class uvm_reg_tlm_adapter extends uvm_reg_adapter
For converting between uvm_reg_bus_op and uvm_tlm_gp items.
class uvm_reg_write_only_cbs extends uvm_reg_cbs
Pre-defined register callback method for write-only registers that will issue an error if a read() operation is attempted.
typedef class uvm_report_catcher
The uvm_report_catcher is used to catch messages issued by the uvm report server.
The uvm_report_handler is the class to which most methods in uvm_report_object delegate.
class uvm_report_object extends uvm_object
The uvm_report_object provides an interface to the UVM reporting facility.
class uvm_report_phase extends uvm_bottomup_phase
Report results of the test.
uvm_report_server is a global server that processes all of the reports generated by an uvm_report_handler.
class uvm_reset_phase extends uvm_task_phase
Reset is asserted.
class uvm_resource #( type  T  =  int ) extends uvm_resource_base
Parameterized resource.
virtual class uvm_resource_base extends uvm_object
Non-parameterized base class for resources.
class uvm_resource_db #( type  T  =  uvm_object )
All of the functions in uvm_resource_db#(T) are static, so they must be called using the :: operator.
Provides a namespace for managing options for the resources DB facility.
Provides a namespace for managing options for the resources facility.
class uvm_resource_pool
The global (singleton) resource database.
class uvm_resource_types
Provides typedefs and enums used throughout the resources facility.
The uvm_root class serves as the implicit top-level and phase controller for all UVM components.
class uvm_run_phase extends uvm_task_phase
Stimulate the DUT.
virtual class uvm_scoreboard extends uvm_component
The uvm_scoreboard virtual class should be used as the base class for user-defined scoreboards.
class uvm_seq_item_pull_export #(
    type  REQ  =  int,
    type  RSP  =  REQ
) extends uvm_port_base #(uvm_sqr_if_base #(REQ, RSP))
This export type is used in sequencer-driver communication.
class uvm_seq_item_pull_imp #(
    type  REQ  =  int,
    type  RSP  =  REQ,
    type  IMP  =  int
) extends uvm_port_base #(uvm_sqr_if_base #(REQ, RSP))
This imp type is used in sequencer-driver communication.
class uvm_seq_item_pull_port #(
    type  REQ  =  int,
    type  RSP  =  REQ
) extends uvm_port_base #(uvm_sqr_if_base #(REQ, RSP))
UVM provides a port, export, and imp connector for use in sequencer-driver communication.
virtual class uvm_sequence #(
    type  REQ  =  uvm_sequence_item,
    type  RSP  =  REQ
) extends uvm_sequence_base
The uvm_sequence class provides the interfaces necessary in order to create streams of sequence items and/or other sequences.
class uvm_sequence_base extends uvm_sequence_item
The uvm_sequence_base class provides the interfaces needed to create streams of sequence items and/or other sequences.
class uvm_sequence_item extends uvm_transaction
The base class for user-defined sequence items and also the base class for the uvm_sequence class.
class uvm_sequencer #(
    type  REQ  =  uvm_sequence_item,
      RSP  =  REQ
) extends uvm_sequencer_param_base #(REQ, RSP)
class uvm_sequencer_base extends uvm_component
Controls the flow of sequences, which generate the stimulus (sequence item transactions) that is passed on to drivers for execution.
class uvm_sequencer_param_base #(
    type  REQ  =  uvm_sequence_item,
    type  RSP  =  REQ
) extends uvm_sequencer_base
Extends uvm_sequencer_base with an API depending on specific request (REQ) and response (RSP) types.
class uvm_shutdown_phase extends uvm_task_phase
Letting things settle down.
virtual class uvm_sqr_if_base #( type  T1  =  uvm_object,
  T2  =  T1 )
This class defines an interface for sequence drivers to communicate with sequencers.
class uvm_start_of_simulation_phase extends uvm_bottomup_phase
Get ready for DUT to be simulated.
virtual class uvm_subscriber #( type  T  =  int ) extends uvm_component
This class provides an analysis export for receiving transactions from a connected analysis export.
class uvm_table_printer extends uvm_printer
The table printer prints output in a tabular format.
virtual class uvm_task_phase extends uvm_phase
Base class for all task phases.
virtual class uvm_test extends uvm_component
This class is the virtual base class for the user-defined tests.
class uvm_tlm_analysis_fifo #( type  T  =  int ) extends uvm_tlm_fifo #(T)
An analysis_fifo is a uvm_tlm_fifo with an unbounded size and a write interface.
class uvm_tlm_b_initiator_socket #(
    type  T  =  uvm_tlm_generic_payload
) extends uvm_tlm_b_initiator_socket_base #(T)
IS-A forward port; has no backward path except via the payload contents
class uvm_tlm_b_initiator_socket_base #(
    type  T  =  uvm_tlm_generic_payload
) extends uvm_port_base #(uvm_tlm_if #(T))
IS-A forward port; has no backward path except via the payload contents
class uvm_tlm_b_passthrough_initiator_socket #(
    type  T  =  uvm_tlm_generic_payload
) extends uvm_tlm_b_passthrough_initiator_socket_base #(T)
IS-A forward port;
class uvm_tlm_b_passthrough_initiator_socket_base #(
    type  T  =  uvm_tlm_generic_payload
) extends uvm_port_base #(uvm_tlm_if #(T))
IS-A forward port
class uvm_tlm_b_passthrough_target_socket #(
    type  T  =  uvm_tlm_generic_payload
) extends uvm_tlm_b_passthrough_target_socket_base #(T)
IS-A forward export;
class uvm_tlm_b_passthrough_target_socket_base #(
    type  T  =  uvm_tlm_generic_payload
) extends uvm_port_base #(uvm_tlm_if #(T))
IS-A forward export
class uvm_tlm_b_target_socket #(
    type  IMP  =  int,
    type  T  =  uvm_tlm_generic_payload
) extends uvm_tlm_b_target_socket_base #(T)
IS-A forward imp; has no backward path except via the payload contents.
class uvm_tlm_b_target_socket_base #(
    type  T  =  uvm_tlm_generic_payload
) extends uvm_port_base #(uvm_tlm_if #(T))
IS-A forward imp; has no backward path except via the payload contents.
class uvm_tlm_b_transport_export #(
    type  T  =  uvm_tlm_generic_payload
) extends uvm_port_base #(uvm_tlm_if #(T))
Blocking transport export class.
class uvm_tlm_b_transport_imp #(
    type  T  =  uvm_tlm_generic_payload,
    type  IMP  =  int
) extends uvm_port_base #(uvm_tlm_if #(T))
Used like exports, except an addtional class parameter specifices the type of the implementation object.
class uvm_tlm_b_transport_port #(
    type  T  =  uvm_tlm_generic_payload
) extends uvm_port_base #(uvm_tlm_if #(T))
Class providing the blocking transport port, The port can be bound to one export.
class uvm_tlm_extension #( type  T  =  int ) extends uvm_tlm_extension_base
TLM extension class.
virtual class uvm_tlm_extension_base extends uvm_object
The class uvm_tlm_extension_base is the non-parameterized base class for all generic payload extensions.
class uvm_tlm_fifo #( type  T  =  int ) extends uvm_tlm_fifo_base #(T)
This class provides storage of transactions between two independently running processes.
virtual class uvm_tlm_fifo_base #( type  T  =  int ) extends uvm_component
This class is the base for uvm_tlm_fifo #(T).
class uvm_tlm_generic_payload extends uvm_sequence_item
This class provides a transaction definition commonly used in memory-mapped bus-based systems.
typedef uvm_tlm_generic_payload uvm_tlm_gp
This typedef provides a short, more convenient name for the uvm_tlm_generic_payload type.
class uvm_tlm_if #( type  T  =  uvm_tlm_generic_payload,
type  P  =  uvm_tlm_phase_e )
Base class type to define the transport functions.
virtual class uvm_tlm_if_base #( type  T1  =  int,
type  T2  =  int )
This class declares all of the methods of the TLM API.
class uvm_tlm_nb_initiator_socket #(
    type  IMP  =  int,
    type  T  =  uvm_tlm_generic_payload,
    type  P  =  uvm_tlm_phase_e
) extends uvm_tlm_nb_initiator_socket_base #(T,P)
IS-A forward port; HAS-A backward imp
class uvm_tlm_nb_initiator_socket_base #(
    type  T  =  uvm_tlm_generic_payload,
    type  P  =  uvm_tlm_phase_e
) extends uvm_port_base #(uvm_tlm_if #(T,P))
IS-A forward port; HAS-A backward imp
class uvm_tlm_nb_passthrough_initiator_socket #(
    type  T  =  uvm_tlm_generic_payload,
    type  P  =  uvm_tlm_phase_e
) extends uvm_tlm_nb_passthrough_initiator_socket_base #(T,P)
IS-A forward port; HAS-A backward export
class uvm_tlm_nb_passthrough_initiator_socket_base #(
    type  T  =  uvm_tlm_generic_payload,
    type  P  =  uvm_tlm_phase_e
) extends uvm_port_base #(uvm_tlm_if #(T,P))
IS-A forward port; HAS-A backward export
class uvm_tlm_nb_passthrough_target_socket #(
    type  T  =  uvm_tlm_generic_payload,
    type  P  =  uvm_tlm_phase_e
) extends uvm_tlm_nb_passthrough_target_socket_base #(T,P)
IS-A forward export; HAS-A backward port
class uvm_tlm_nb_passthrough_target_socket_base #(
    type  T  =  uvm_tlm_generic_payload,
    type  P  =  uvm_tlm_phase_e
) extends uvm_port_base #(uvm_tlm_if #(T,P))
IS-A forward export; HAS-A backward port
class uvm_tlm_nb_target_socket #(
    type  IMP  =  int,
    type  T  =  uvm_tlm_generic_payload,
    type  P  =  uvm_tlm_phase_e
) extends uvm_tlm_nb_target_socket_base #(T,P)
IS-A forward imp; HAS-A backward port
class uvm_tlm_nb_target_socket_base #(
    type  T  =  uvm_tlm_generic_payload,
    type  P  =  uvm_tlm_phase_e
) extends uvm_port_base #(uvm_tlm_if #(T,P))
IS-A forward imp; HAS-A backward port
class uvm_tlm_nb_transport_bw_export #(
    type  T  =  uvm_tlm_generic_payload,
    type  P  =  uvm_tlm_phase_e
) extends uvm_port_base #(uvm_tlm_if #(T,P))
Non-blocking backward transport export class
class uvm_tlm_nb_transport_bw_imp #(
    type  T  =  uvm_tlm_generic_payload,
    type  P  =  uvm_tlm_phase_e,
    type  IMP  =  int
) extends uvm_port_base #(uvm_tlm_if #(T,P))
Used like exports, except an addtional class parameter specifices the type of the implementation object.
class uvm_tlm_nb_transport_bw_port #(
    type  T  =  uvm_tlm_generic_payload,
    type  P  =  uvm_tlm_phase_e
) extends uvm_port_base #(uvm_tlm_if #(T,P))
Class providing the non-blocking backward transport port.
class uvm_tlm_nb_transport_fw_export #(
    type  T  =  uvm_tlm_generic_payload,
    type  P  =  uvm_tlm_phase_e
) extends uvm_port_base #(uvm_tlm_if #(T,P))
Non-blocking forward transport export class
class uvm_tlm_nb_transport_fw_imp #(
    type  T  =  uvm_tlm_generic_payload,
    type  P  =  uvm_tlm_phase_e,
    type  IMP  =  int
) extends uvm_port_base #(uvm_tlm_if #(T,P))
Used like exports, except an addtional class parameter specifices the type of the implementation object.
class uvm_tlm_nb_transport_fw_port #(
    type  T  =  uvm_tlm_generic_payload,
    type  P  =  uvm_tlm_phase_e
) extends uvm_port_base #(uvm_tlm_if #(T,P))
Class providing the non-blocking backward transport port.
class uvm_tlm_req_rsp_channel #( type  REQ  =  int,
type  RSP  =  REQ ) extends uvm_component
The uvm_tlm_req_rsp_channel contains a request FIFO of type REQ and a response FIFO of type RSP.
class uvm_tlm_time
Canonical time type that can be used in different timescales
class uvm_tlm_transport_channel #(
    type  REQ  =  int,
    type  RSP  =  REQ
) extends uvm_tlm_req_rsp_channel #(REQ, RSP)
A uvm_tlm_transport_channel is a uvm_tlm_req_rsp_channel #(REQ,RSP) that implements the transport interface.
virtual class uvm_topdown_phase extends uvm_phase
Virtual base class for function phases that operate top-down.
virtual class uvm_transaction extends uvm_object
The uvm_transaction class is the root base class for UVM transactions.
class uvm_tree_printer extends uvm_printer
By overriding various methods of the uvm_printer super class, the tree printer prints output in a tree format.
class uvm_utils #( type  TYPE  =  int,
string  FIELD  =  "config" )
This class contains useful template functions.
class uvm_vreg extends uvm_object
Virtual register abstraction base class
class uvm_vreg_cbs extends uvm_callback
Pre/post read/write callback facade class
class uvm_vreg_field extends uvm_object
Virtual field abstraction class
class uvm_vreg_field_cbs extends uvm_callback
Pre/post read/write callback facade class