Index
$#! · 0-9 · A · B · C · D · E · F · G · H · I · J · K · L · M · N · O · P · Q · R · S · T · U · V · W · X · Y · Z
$#!
 +UVM_CONFIG_DB_TRACE
 +UVM_DUMP_CMDLINE_ARGS
 +UVM_MAX_QUIT_COUNT
 +UVM_OBJECTION_TRACE
 +UVM_PHASE_TRACE
 +UVM_RESOURCE_DB_TRACE
 +uvm_set_action
 +uvm_set_config_int,+uvm_set_config_string
 +uvm_set_inst_override,+uvm_set_type_override
 +uvm_set_severity
 +uvm_set_verbosity
 +UVM_TESTNAME
 +UVM_TIMEOUT
 +UVM_VERBOSITY
 `uvm_analysis_imp_decl
 `uvm_blocking_get_imp_decl
 `uvm_blocking_get_peek_imp_decl
 `uvm_blocking_master_imp_decl
 `uvm_blocking_peek_imp_decl
 `uvm_blocking_put_imp_decl
 `uvm_blocking_slave_imp_decl
 `uvm_blocking_transport_imp_decl
 `uvm_component_end
 `uvm_component_param_utils
 `uvm_component_param_utils_begin
 `uvm_component_registry
 `uvm_component_utils
 `uvm_component_utils_begin
 `uvm_create
 `uvm_create_on
 `uvm_declare_p_sequencer
 `UVM_DEFAULT_TIMEOUT
 `uvm_do
 `uvm_do_callbacks
 `uvm_do_callbacks_exit_on
 `uvm_do_obj_callbacks
 `uvm_do_obj_callbacks_exit_on
 `uvm_do_on
 `uvm_do_on_pri
 `uvm_do_on_pri_with
 `uvm_do_on_with
 `uvm_do_pri
 `uvm_do_pri_with
 `uvm_do_with
 `uvm_error
 `uvm_error_context
 `uvm_fatal
 `uvm_fatal_context
 `uvm_field_*macro flags
 `uvm_field_*macros
 `uvm_field_aa_*_int macros
 `uvm_field_aa_*_string macros
 `uvm_field_aa_int_byte
 `uvm_field_aa_int_byte_unsigned
 `uvm_field_aa_int_enumkey
 `uvm_field_aa_int_int
 `uvm_field_aa_int_int_unsigned
 `uvm_field_aa_int_integer
 `uvm_field_aa_int_integer_unsigned
 `uvm_field_aa_int_key
 `uvm_field_aa_int_longint
 `uvm_field_aa_int_longint_unsigned
 `uvm_field_aa_int_shortint
 `uvm_field_aa_int_shortint_unsigned
 `uvm_field_aa_int_string
 `uvm_field_aa_object_int
 `uvm_field_aa_object_string
 `uvm_field_aa_string_string
 `uvm_field_array_*macros
 `uvm_field_array_enum
 `uvm_field_array_int
 `uvm_field_array_object
 `uvm_field_array_string
 `uvm_field_enum
 `uvm_field_event
 `uvm_field_int
 `uvm_field_object
 `uvm_field_queue_*macros
 `uvm_field_queue_enum
 `uvm_field_queue_int
 `uvm_field_queue_object
 `uvm_field_queue_string
 `uvm_field_real
 `uvm_field_sarray_*macros
 `uvm_field_sarray_enum
 `uvm_field_sarray_int
 `uvm_field_sarray_object
 `uvm_field_sarray_string
 `uvm_field_string
 `uvm_field_utils_begin
 `uvm_field_utils_end
 `uvm_get_imp_decl
 `uvm_get_peek_imp_decl
 `uvm_info
 `uvm_info_context
 `uvm_master_imp_decl
 `UVM_MAX_STREAMBITS
 `uvm_nonblocking_get_imp_decl
 `uvm_nonblocking_get_peek_imp_decl
 `uvm_nonblocking_master_imp_decl
 `uvm_nonblocking_peek_imp_decl
 `uvm_nonblocking_put_imp_decl
 `uvm_nonblocking_slave_imp_decl
 `uvm_nonblocking_transport_imp_decl
 `uvm_object_param_utils
 `uvm_object_param_utils_begin
 `uvm_object_registry
 `uvm_object_utils
 `uvm_object_utils_begin
 `uvm_object_utils_end
 `uvm_pack_array
 `uvm_pack_arrayN
 `uvm_pack_enum
 `uvm_pack_enumN
 `uvm_pack_int
 `uvm_pack_intN
 `uvm_pack_queue
 `uvm_pack_queueN
 `uvm_pack_real
 `uvm_pack_sarray
 `uvm_pack_sarrayN
 `uvm_pack_string
 `UVM_PACKER_MAX_BYTES
 `uvm_peek_imp_decl
 `uvm_put_imp_decl
 `uvm_rand_send
 `uvm_rand_send_pri
 `uvm_rand_send_pri_with
 `uvm_rand_send_with
 `uvm_record_attribute
 `uvm_record_field
 `UVM_REG_ADDR_WIDTH
 `UVM_REG_BYTENABLE_WIDTH
 `UVM_REG_CVR_WIDTH
 `UVM_REG_DATA_WIDTH
 `uvm_register_cb
 `uvm_send
 `uvm_send_pri
 `uvm_set_super_type
 `uvm_slave_imp_decl
 `UVM_TLM_B_MASK
 `UVM_TLM_B_TRANSPORT_IMP
 `UVM_TLM_FUNCTION_ERROR
 `UVM_TLM_NB_BW_MASK
 `UVM_TLM_NB_FW_MASK
 `UVM_TLM_NB_TRANSPORT_BW_IMP
 `UVM_TLM_NB_TRANSPORT_FW_IMP
 `UVM_TLM_TASK_ERROR
 `uvm_transport_imp_decl
 `uvm_unpack_array
 `uvm_unpack_arrayN
 `uvm_unpack_enum
 `uvm_unpack_enumN
 `uvm_unpack_int
 `uvm_unpack_intN
 `uvm_unpack_queue
 `uvm_unpack_queueN
 `uvm_unpack_real
 `uvm_unpack_sarray
 `uvm_unpack_sarrayN
 `uvm_unpack_string
 `uvm_warning
 `uvm_warning_context
A
 abstract
 abstractions
 accept_tr
 Access
 accessors
 adapter
 add
 Add/ delete inteface
 add_by_name
 add_callback
 add_coverage
 add_hdl_path
 add_hdl_path_slice
 add_mem
 add_path
 add_reg
 add_slice
 add_submap
 add_uvm_phases
 addr
 adjust_name
 after_export
 all_dropped
 alloc_mode_e
 allocate
 Analysis
 Analysis Ports
 analysis_export
 analysis_export#(T)
 apply_config_settings
 Argument Values
 Audit Trail
B
 b_transport
 Backdoor
 backdoor_read
 backdoor_read_func
 backdoor_watch
 backdoor_write
 BASE
 Basic Arguments
 bd_kind
 before_export
 begin_child_tr
 begin_elements
 begin_event
 BEGIN_REQ
 BEGIN_RESP
 begin_tr
 Bidirectional Interfaces&Ports
 big_endian
 bin_radix
 Bit Bashing Test Sequences
 Blocking get
 Blocking peek
 Blocking put
 Blocking transport
 blocking_put_port
 body
 BODY
 build_coverage
 build_phase
 Built-in UVM Aware Command Line Arguments
 burst_read
 burst_write
 Bus Access
 bus_in
 bus2reg
 byte_en
C
 Callback Hooks
 Callback Interface
 Callback Macros
 callback_mode
 Callbacks
 Callbacks Classes
 can_get
 can_peek
 can_put
 cancel
 capacity
 catch
 CB
 Change Message State
 check_config_usage
 check_data_width
 check_phase
 check_type
 Classes for Adapting Between Register and Bus Operations
 clear
 clear_extension
 clear_extensions
 clear_hdl_path
 clear_response_queue
 clone
 Command Line Debug
 Command Line Processor Class
 Comparators
 compare
 compare_field
 compare_field_int
 compare_field_real
 compare_object
 compare_string
 Comparing
 compose_message
 Configuration
 Configuration and Resource Classes
 Configuration Interface
 configure
 configure_phase
 connect
 Connect
 connect_phase
 Construction
 Container Classes
 Convenience Write/ Read API
 convert2string
 copy
 Copying
 Core Base Classes
 Coverage
 create
 create_component
 create_component_by_name
 create_component_by_type
 create_item
 create_map
 create_object
 create_object_by_name
 create_object_by_type
 CREATED
 Creation
 Current Message State
 current_grabber
+UVM_CONFIG_DB_TRACE turns on tracing of configuration DB access.
+UVM_DUMP_CMDLINE_ARGS allows the user to dump all command line arguments to the reporting mechanism.
+UVM_MAX_QUIT_COUNT=<count>,<overridable> allows users to change max quit count for the report server.
+UVM_OBJECTION_TRACE turns on tracing of objection activity.
+UVM_PHASE_TRACE turns on tracing of phase executions.
+UVM_RESOURCE_DB_TRACE turns on tracing of resource DB access.
+uvm_set_action=<comp>,<id>,<severity>,<action> provides the equivalent of various uvm_report_object’s set_report_*_action APIs.
+uvm_set_config_int=<comp>,<field>,<value> and +uvm_set_config_string=<comp>,<field>,<value> work like their procedural counterparts: set_config_int() and set_config_string().
+uvm_set_inst_override=<req_type>,<override_type>,<full_inst_path> and +uvm_set_type_override=<req_type>,<override_type>[,<replace>] work like the name based overrides in the factory--factory.set_inst_override_by_name() and factory.set_type_override_by_name().
+uvm_set_severity=<comp>,<id>,<current severity>,<new severity> provides the equivalent of the various uvm_report_object’s set_report_*_severity_override APIs.
+uvm_set_verbosity=<comp>,<id>,<verbosity>,<phase> and +uvm_set_verbosity=<comp>,<id>,<verbosity>,time,<time> allow the users to manipulate the verbosity of specific components at specific phases (and times during the “run” phases) of the simulation.
+UVM_TESTNAME=<class name> allows the user to specify which uvm_test (or uvm_component) should be created via the factory and cycled through the UVM phases.
+UVM_TIMEOUT=<timeout>,<overridable> allows users to change the global timeout of the UVM framework.
+UVM_VERBOSITY=<verbosity> allows the user to specify the initial verbosity for all components.
uvm_component-based class declarations may contain one of the above forms of utility macros.
Registers a uvm_component-based class with the factory
This macro is used to declare a variable p_sequencer whose type is specified by SEQUENCER.
The default timeout for all phases, if not overridden by uvm_root::set_timeout or +UVM_TIMEOUT
Defines what operations a given field should be involved in.
Macros that implement data operations for scalar properties.
Macros that implement data operations for associative arrays indexed by an integral type.
Macros that implement data operations for associative arrays indexed by string.
Implements the data operations for an associative array of integral types indexed by the byte data type.
Implements the data operations for an associative array of integral types indexed by the byte unsigned data type.
Implements the data operations for an associative array of integral types indexed by any enumeration key data type.
Implements the data operations for an associative array of integral types indexed by the int data type.
Implements the data operations for an associative array of integral types indexed by the int unsigned data type.
Implements the data operations for an associative array of integral types indexed by the integer data type.
Implements the data operations for an associative array of integral types indexed by the integer unsigned data type.
Implements the data operations for an associative array of integral types indexed by any integral key data type.
Implements the data operations for an associative array of integral types indexed by the longint data type.
Implements the data operations for an associative array of integral types indexed by the longint unsigned data type.
Implements the data operations for an associative array of integral types indexed by the shortint data type.
Implements the data operations for an associative array of integral types indexed by the shortint unsigned data type.
Implements the data operations for an associative array of integrals indexed by string.
Implements the data operations for an associative array of uvm_object-based objects indexed by the int data type.
Implements the data operations for an associative array of uvm_object-based objects indexed by string.
Implements the data operations for an associative array of strings indexed by string.
Macros that implement data operations for one-dimensional dynamic array properties.
Implements the data operations for a one-dimensional dynamic array of enums.
Implements the data operations for a one-dimensional dynamic array of integrals.
Implements the data operations for a one-dimensional dynamic array of uvm_object-based objects.
Implements the data operations for a one-dimensional dynamic array of strings.
Implements the data operations for an enumerated property.
Implements the data operations for an event property.
Implements the data operations for any packed integral property.
Implements the data operations for an uvm_object-based property.
Macros that implement data operations for dynamic queues.
Implements the data operations for a one-dimensional queue of enums.
Implements the data operations for a queue of integrals.
Implements the data operations for a queue of uvm_object-based objects.
Implements the data operations for a queue of strings.
Implements the data operations for any real property.
Macros that implement data operations for one-dimensional static array properties.
Implements the data operations for a one-dimensional static array of enums.
Implements the data operations for a one-dimensional static array of integrals.
Implements the data operations for a one-dimensional static array of uvm_object-based objects.
Implements the data operations for a one-dimensional static array of strings.
Implements the data operations for a string property.
These macros form a block in which `uvm_field_* macros can be placed.
Defines the maximum bit vector size for integral types.
Register a uvm_object-based class with the factory
uvm_object-based class declarations may contain one of the above forms of utility macros.
Pack a dynamic array without having to also specify the bit size of its elements.
Pack a dynamic array of integrals.
Pack an enumeration value.
Pack an integral variable.
Pack an integral variable without having to also specify the bit size.
Pack an integral variable.
Pack a queue without having to also specify the bit size of its elements.
Pack a queue of integrals.
Pack a variable of type real.
Pack a static array without having to also specify the bit size of its elements.
Pack a static array of integrals.
Pack a string variable.
Defines the maximum bytes to allocate for packing an object using the uvm_packer.
Vendor-independent macro for recording attributes (fields) to a vendor-specific transaction database.
Macro for recording name-value pairs into a transaction recording database.
Maximum address width in bits
Maximum number of byte enable bits
Maximum number of bits in a uvm_reg_cvr_t coverage model set.
Maximum data width in bits
Define blocking mask onehot assignment = ‘b100
The macro wraps the function b_transport() Execute a blocking transaction.
Defines Not-Yet-Implemented TLM functions
Define Non blocking backward mask onehot assignment = ‘b010
Define Non blocking Forward mask onehot assignment = ‘b001
Implementation of the backward path.
The macro wraps the forward path call function nb_transport_fw()
Defines Not-Yet-Implemented TLM tasks
Unpack a dynamic array without having to also specify the bit size of its elements.
Unpack into a dynamic array of integrals.
Unpack an enumeration value, which requires its type be specified.
Unpack enum of type TYPE into VAR.
Unpack an integral variable without having to also specify the bit size.
Unpack into an integral variable.
Unpack a queue without having to also specify the bit size of its elements.
Unpack into a queue of integrals.
Unpack a variable of type real.
Unpack a static array without having to also specify the bit size of its elements.
Unpack a static (fixed) array of integrals.
Pack a string variable.
bit abstract = 1
This bit provides a filtering mechanism for fields.
bit abstract = 0
This bit provides a filtering mechanism for fields.
bit abstract = 1
This bit provides a filtering mechanism for fields.
string abstractions[$]
If set, check the HDL paths for the specified design abstractions.
function void accept_tr ( uvm_transaction  tr,   
time  accept_time  =  )
This function marks the acceptance of a transaction, tr, by this component.
function void accept_tr ( time  accept_time  =  )
Calling accept_tr indicates that the transaction item has been received by a consumer component.
The accessor functions let you set and get each of the members of the generic payload.
uvm_reg_adapter adapter
The adapter used to convey the parameters of a bus operation in terms of a canonical uvm_reg_bus_op datum.
uvm_reg_adapter adapter
Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.
static function void add( obj,   
uvm_callback  cb,   
uvm_apprepend  ordering  =  UVM_APPEND )
Registers the given callback object, cb, with the given obj handle.
function void add ( uvm_component  comp )
Add a single component to the set of components to be monitored.
function void add( uvm_phase  phase,   
uvm_phase  with_phase  =  null,
uvm_phase  after_phase  =  null,
uvm_phase  before_phase  =  null )
Build up a schedule structure inserting phase by phase, specifying linkage
virtual function void add ( KEY  key,
item )
Adds the given (key, item) pair to the pool.
static function void add( uvm_reg  rg )
Add this callback to the specified register and its contained fields.
static function void add( uvm_reg  rg )
Add this callback to the specified register and its contained fields.
static function void add_by_name( string  name,   
uvm_callback  cb,   
uvm_component  root,   
uvm_apprepend  ordering  =  UVM_APPEND )
Registers the given callback object, cb, with one or more uvm_components.
virtual function void add_callback ( uvm_event_callback  cb,   
bit  append  =  1 )
Registers a callback object, cb, with this event.
virtual protected function void add_coverage( uvm_reg_cvr_t  models )
Specify that additional coverage models are available.
virtual protected function void add_coverage( uvm_reg_cvr_t  models )
Specify that additional coverage models are available.
virtual protected function void add_coverage( uvm_reg_cvr_t  models )
Specify that additional coverage models are available.
function void add_hdl_path ( uvm_hdl_path_slice  slices[],   
string  kind  =  "RTL" )
Add an HDL path
function void add_hdl_path ( uvm_hdl_path_slice  slices[],   
string  kind  =  "RTL" )
Add an HDL path
function void add_hdl_path ( string  path,   
string  kind  =  "RTL" )
Add an HDL path
function void add_hdl_path ( string  path,   
string  kind  =  "RTL" )
Add an HDL path
function void add_hdl_path_slice( string  name,   
int  offset,   
int  size,   
bit  first  =  0,
string  kind  =  "RTL" )
Add the specified HDL slice to the HDL path for the specified design abstraction.
function void add_hdl_path_slice( string  name,   
int  offset,   
int  size,   
bit  first  =  0,
string  kind  =  "RTL" )
Append the specified HDL slice to the HDL path of the register instance for the specified design abstraction.
virtual function void add_mem ( uvm_mem  mem,   
uvm_reg_addr_t  offset,   
string  rights  =  "RW",
bit  unmapped  =  0,
uvm_reg_frontdoor  frontdoor  =  null )
Add a memory
function void add_path( string  path,   
int  unsigned  offset  =  -1,
int  unsigned  size  =  -1 )
Append the specified path to the path concatenation, for the specified number of bits at the specified offset.
virtual function void add_reg ( uvm_reg  rg,   
uvm_reg_addr_t  offset,   
string  rights  =  "RW",
bit  unmapped  =  0,
uvm_reg_frontdoor  frontdoor  =  null )
Add a register
function void add_slice( uvm_hdl_path_slice  slice )
Append the specified slice literal to the path concatenation
virtual function void add_submap ( uvm_reg_map  child_map,
uvm_reg_addr_t  offset )
Add an address map
static function void add_uvm_phases( uvm_phase  schedule )
Appends to the given schedule the built-in UVM phases.
uvm_reg_addr_t addr
The bus address.
virtual protected function string adjust_name ( string  id,   
byte  scope_separator  =  "." )
Prints a field’s name, or id, which is the full instance name.
The export to which a data stream of type AFTER is sent via a connected analysis port.
The export to which the other stream of data is written.
virtual task all_dropped ( uvm_object  obj,
uvm_object  source_obj,
string  description,
int  count )
Executes the uvm_objection_callback::all_dropped task in the user callback class whenever the objection count for this objection in reference to obj goes to zero.
virtual task all_dropped ( uvm_objection  objection,
uvm_object  source_obj,
string  description,
int  count )
The all_droppped callback is called when all objections have been dropped by this component and all its descendants.
virtual task all_dropped ( uvm_object  obj,
uvm_object  source_obj,
string  description,
int  count )
Objection callback that is called when a drop_objection has reached obj, and the total count for obj goes to zero.
virtual task all_dropped ( uvm_objection  objection,
uvm_object  obj,
uvm_object  source_obj,
string  description,
int  count )
Objection all_dropped callback function.
Memory allocation mode
virtual function uvm_mem_region allocate( longint  unsigned  n,
uvm_mem_mam  mam )
Randomly implement, resize or relocate a virtual register array
The analysis interface is used to perform non-blocking broadcasts of transactions to connected components.
This section defines the port, export, and imp classes used for transaction analysis.
This export provides access to the write method, which derived subscribers must implement.
The analysis_export provides the write method to all connected analysis ports and parent exports:
virtual function void apply_config_settings ( bit  verbose  =  )
Searches for all config settings matching this component’s instance path.
To find out what is happening as the simulation proceeds, an audit trail of each read and write is kept.
virtual task b_transport( t,
uvm_tlm_time  delay )
Execute a blocking transaction.
virtual protected task backdoor_read( uvm_reg_item  rw )
User-define backdoor read access
virtual task backdoor_read( uvm_reg_item  rw )
User-define backdoor read access
virtual function uvm_status_e backdoor_read_func( uvm_reg_item  rw )
User-defined backdoor read access
virtual function uvm_status_e backdoor_read_func( uvm_reg_item  rw )
User-defined backdoor read access
virtual task backdoor_watch()
User-defined DUT register change monitor
virtual task backdoor_write( uvm_reg_item  rw )
User-defined backdoor read access
virtual task backdoor_write( uvm_reg_item  rw )
User-defined backdoor read access
Specifies the sequence type to extend from.
string bd_kind = ""
If path is UVM_BACKDOOR, this member specifies the abstraction kind for the backdoor access, e.g.
The export to which a data stream of type BEFORE is sent via a connected analysis port.
The export to which one stream of data is written.
function integer begin_child_tr ( uvm_transaction  tr,   
integer  parent_handle  =  0,
string  stream_name  =  "main",
string  label  =  "",
string  desc  =  "",
time  begin_time  =  0 )
This function marks the start of a child transaction, tr, by this component.
function integer begin_child_tr ( time  begin_time  =  0,
integer  parent_handle  =  0 )
This function indicates that the transaction has been started as a child of a parent transaction given by parent_handle.
int begin_elements = 5
Defines the number of elements at the head of a list to print.
uvm_event begin_event
A uvm_event that is triggered when this transaction’s actual execution on the bus begins, typically as a result of a driver calling uvm_component::begin_tr.
Beginning of request phase
Begining of response phase
function integer begin_tr ( uvm_transaction  tr,   
string  stream_name  =  "main",
string  label  =  "",
string  desc  =  "",
time  begin_time  =  0,
integer  parent_handle  =  0 )
This function marks the start of a transaction, tr, by this component.
function integer begin_tr ( time  begin_time  =  )
This function indicates that the transaction has been started and is not the child of another transaction.
The bidirectional interfaces consist of blocking, non-blocking, and combined blocking and non-blocking variants of the transport, master, and slave interfaces.
bit big_endian = 1
This bit determines the order that integral data is packed (using pack_field, pack_field_int, pack_time, or pack_real) and how the data is unpacked from the pack array (using unpack_field, unpack_field_int, unpack_time, or unpack_real).
string bin_radix = "'b"
This string should be prepended to the value of an integral type when a radix of UVM_BIN is used for the radix of the integral object.
This section defines classes that test individual bits of the registers defined in a register model.
The blocking_put_port is used to send the generated stimulus to the rest of the testbench.
virtual task body()
Execute the Memory Access sequence.
virtual task body()
Performs the walking-ones algorithm on each map of the memory specifed in mem.
virtual task body()
Executes the mem walk sequence, one block at a time.
virtual task body()
Executes the Register Access sequence.
virtual task body()
Executes the Register Bit Bash sequence.
virtual task body()
Executes the Hardware Reset sequence.
virtual task body()
Executes any or all the built-in register and memory sequences.
virtual task body()
Executes the Shared Register and Memory sequence
virtual task body()
Continually gets a register transaction from the configured upstream sequencer, reg_seqr, and executes the corresponding bus transaction via do_rw_access.
virtual task body()
This is the user-defined task where the main sequence code resides.
The sequence is started and the uvm_sequence_base::body() task is being executed.
protected function uvm_reg_cvr_t build_coverage( uvm_reg_cvr_t  models )
Check if all of the specified coverage model must be built.
protected function uvm_reg_cvr_t build_coverage( uvm_reg_cvr_t  models )
Check if all of the specified coverage models must be built.
protected function uvm_reg_cvr_t build_coverage( uvm_reg_cvr_t  models )
Check if all of the specified coverage model must be built.
virtual function void build_phase( uvm_phase  phase )
The uvm_build_phase phase implementation method.
virtual task burst_read( output  uvm_status_e  status,   
input  uvm_reg_addr_t  offset,   
output  uvm_reg_data_t  value[],   
input  uvm_path_e  path  =  UVM_DEFAULT_PATH,
input  uvm_reg_map  map  =  null,
input  uvm_sequence_base  parent  =  null,
input  int  prior  =  -1,
input  uvm_object  extension  =  null,
input  string  fname  =  "",
input  int  lineno  =  0 )
Read values from memory locations
task burst_read( output  uvm_status_e  status,   
input  uvm_reg_addr_t  offset,   
output  uvm_reg_data_t  value[],   
input  uvm_path_e  path  =  UVM_DEFAULT_PATH,
input  uvm_reg_map  map  =  null,
input  uvm_sequence_base  parent  =  null,
input  int  prior  =  -1,
input  uvm_object  extension  =  null,
input  string  fname  =  "",
input  int  lineno  =  0 )
Read from a set of memory location in the region.
virtual task burst_write( output  uvm_status_e  status,   
input  uvm_reg_addr_t  offset,   
input  uvm_reg_data_t  value[],   
input  uvm_path_e  path  =  UVM_DEFAULT_PATH,
input  uvm_reg_map  map  =  null,
input  uvm_sequence_base  parent  =  null,
input  int  prior  =  -1,
input  uvm_object  extension  =  null,
input  string  fname  =  "",
input  int  lineno  =  0 )
Write the specified values in memory locations
task burst_write( output  uvm_status_e  status,   
input  uvm_reg_addr_t  offset,   
input  uvm_reg_data_t  value[],   
input  uvm_path_e  path  =  UVM_DEFAULT_PATH,
input  uvm_reg_map  map  =  null,
input  uvm_sequence_base  parent  =  null,
input  int  prior  =  -1,
input  uvm_object  extension  =  null,
input  string  fname  =  "",
input  int  lineno  =  0 )
Write to a set of memory location in the region.
uvm_analysis_imp #(   BUSTYPE,
uvm_reg_predictor  #(BUSTYPE) ) bus_in
Observed bus transactions of type BUSTYPE are received from this port and processed.
pure virtual function void bus2reg( uvm_sequence_item  bus_item,
ref  uvm_reg_bus_op  rw )
Extensions of this class must implement this method to copy members of the given bus-specific bus_item to corresponding members of the provided bus_rw instance.
virtual function void bus2reg( uvm_sequence_item  bus_item,
ref  uvm_reg_bus_op  rw )
Converts a uvm_tlm_gp item to a uvm_reg_bus_op.
uvm_reg_byte_en_t byte_en
Enables for the byte lanes on the bus.
These macros are used to register and execute callbacks extending from uvm_callbacks.
function bit callback_mode( int  on  =  -1 )
Enable/disable callbacks (modeled like rand_mode and constraint_mode).
This section defines the classes used for callback registration, management, and user-defined callbacks.
virtual function bit can_get()
Returns 1 if a new transaction can be provided immediately upon request, 0 otherwise.
virtual function bit can_peek()
Returns 1 if a new transaction is available; 0 otherwise.
virtual function bit can_put()
Returns 1 if the component is ready to accept the transaction; 0 otherwise.
virtual function void cancel ()
Decrements the waiter count by one.
virtual function void cancel ()
Decrements the number of waiters on the event.
function int unsigned capacity()
The maximum number of entries, or depth, of the FIFO.
pure virtual function action_e catch()
This is the method that is called for each registered report catcher.
This type parameter specifies the base callback type that will be managed by this callback class.
function void check_config_usage ( bit  recurse  =  1 )
Check all configuration settings in a components configuration table to determine if the setting has been used, overridden or not used.
protected static function bit check_data_width( int  unsigned  width )
Check that the specified data width (in bits) is less than or equal to the value of `UVM_REG_DATA_WIDTH
virtual function void check_phase( uvm_phase  phase )
The uvm_check_phase phase implementation method.
virtual function void check_phase( uvm_phase  phase )
Checks that no pending register transactions are still enqueued.
bit check_type = 1
This bit determines whether the type, given by uvm_object::get_type_name, is used to verify that the types of two objects are the same.
This section defines classes used to convert transaction streams between generic register address/data reads and writes and physical bus accesses.
virtual function void clear( uvm_object  obj  =  null )
Immediately clears the objection state.
function void clear_extension( uvm_tlm_extension_base  ext_handle )
Remove the instance-specific extension bound under the specified key.
function void clear_extensions()
Remove all instance-specific extensions
function void clear_hdl_path ( string  kind  =  "RTL" )
Delete HDL paths
function void clear_hdl_path ( string  kind  =  "RTL" )
Delete HDL paths
function void clear_hdl_path ( string  kind  =  "RTL" )
Delete HDL paths
function void clear_hdl_path ( string  kind  =  "RTL" )
Delete HDL paths
virtual function void clear_response_queue()
Empties the response queue for this sequence.
virtual function uvm_object clone ()
The clone method creates and returns an exact copy of this object.
This class provides a general interface to the command line arguments that were provided for the given simulation.
A common function of testbenches is to compare streams of transactions for equivalence.
function bit compare ( uvm_object  rhs,   
uvm_comparer  comparer  =  null )
Deep compares members of this data object with those of the object provided in the rhs (right-hand side) argument, returning 1 on a match, 0 othewise.
virtual function bit compare_field ( string  name,   
uvm_bitstream_t  lhs,   
uvm_bitstream_t  rhs,   
int  size,   
uvm_radix_enum  radix  =  UVM_NORADIX )
Compares two integral values.
virtual function bit compare_field_int ( string  name,   
logic[63:0]  lhs,   
logic[63:0]  rhs,   
int  size,   
uvm_radix_enum  radix  =  UVM_NORADIX )
This method is the same as compare_field except that the arguments are small integers, less than or equal to 64 bits.
virtual function bit compare_field_real ( string  name,
real  lhs,
real  rhs )
This method is the same as compare_field except that the arguments are real numbers.
virtual function bit compare_object ( string  name,
uvm_object  lhs,
uvm_object  rhs )
Compares two class objects using the policy knob to determine whether the comparison should be deep, shallow, or reference.
virtual function bit compare_string ( string  name,
string  lhs,
string  rhs )
Compares two string variables.
virtual function string compose_message( uvm_severity  severity,
string  name,
string  id,
string  message,
string  filename,
int  line )
Constructs the actual string sent to the file or command line from the severity, component name, report id, and the message itself.
The configuration and resources classes provide access to a centralized database where type specific information can be stored and recieved.
Components can be designed to be user-configurable in terms of its topology (the type and number of children it has), mode of operation, and run-time parameters (knobs).
function void configure ( uvm_reg_block  parent,   
string  hdl_path  =  "" )
Instance-specific configuration
function void configure ( uvm_reg_block  blk_parent,   
uvm_reg_file  regfile_parent  =  null,
string  hdl_path  =  "" )
Instance-specific configuration
function void configure( uvm_reg_block  parent  =  null,
string  hdl_path  =  "" )
Instance-specific configuration
function void configure( uvm_reg  parent,
int  unsigned  size,
int  unsigned  lsb_pos,
string  access,
bit  volatile,
uvm_reg_data_t  reset,
bit  has_reset,
bit  is_rand,
bit  individually_accessible )
Instance-specific configuration
function void configure ( uvm_reg_block  blk_parent,   
uvm_reg_file  regfile_parent,   
string  hdl_path  =  "" )
Configure a register file instance
function void configure ( uvm_reg  idx,   
uvm_reg  reg_a[],   
uvm_reg_block  blk_parent,   
uvm_reg_file  regfile_parent  =  null )
Configure the indirect data register.
function void configure( uvm_reg_block  parent,   
uvm_reg_addr_t  base_addr,   
int  unsigned  n_bytes,   
uvm_endianness_e  endian,   
bit  byte_addressing  =  1 )
Instance-specific configuration
function void configure( uvm_reg_block  parent,   
uvm_mem  mem  =  null,
longint  unsigned  size  =  0,
uvm_reg_addr_t  offset  =  0,
int  unsigned  incr  =  0 )
Instance-specific configuration
function void configure( uvm_vreg  parent,
int  unsigned  size,
int  unsigned  lsb_pos )
Instance-specific configuration
virtual task configure_phase( uvm_phase  phase )
The uvm_configure_phase phase implementation method.
virtual function void connect ( this_type  provider )
Connects this port to the given provider port.
function void connect( this_type  provider )
Connect this socket to the specified uvm_tlm_nb_initiator_socket
function void connect( this_type  provider )
Connect this socket to the specified uvm_tlm_nb_initiator_socket
Connect this socket to the specified uvm_tlm_b_target_socket
Connect this socket to the specified uvm_tlm_b_initiator_socket
Connect this socket to the specified uvm_tlm_nb_target_socket
virtual function void connect_phase( uvm_phase  phase )
The uvm_connect_phase phase implementation method.
The container classes are type parameterized datastructures.
The following methods delegate to the corresponding method in the register or memory element.
function string convert2string()
Image of the state of the manager
virtual function string convert2string()
This virtual function is a user-definable hook, called directly by the user, that allows users to provide object information in the form of a string.
virtual function string convert2string()
Returns a string showing the contents of this transaction.
function string convert2string()
Convert the contents of the class to a string suitable for printing.
function void copy ( uvm_object  rhs )
The copy makes this object a copy of the specified object.
The UVM library defines a set of base classes and utilities that facilitate the design of modular, scalable, reusable verification environments.
static function T create( string  name,   
uvm_component  parent,   
string  contxt  =  "" )
Returns an instance of the component type, T, represented by this proxy, subject to any factory overrides based on the context provided by the parent’s full name.
virtual function uvm_object create ( string  name  =  "" )
The create method allocates a new object of the same type as this object and returns it via a base uvm_object handle.
static function T create ( string  name  =  "",
uvm_component  parent  =  null,
string  contxt  =  "" )
Returns an instance of the object type, T, represented by this proxy, subject to any factory overrides based on the context provided by the parent’s full name.
virtual function uvm_object create ( string  name  =  "" )
function uvm_component create_component ( string  requested_type_name,
string  name )
A convenience function for uvm_factory::create_component_by_name, this method calls upon the factory to create a new child component whose type corresponds to the preregistered type name, requested_type_name, and instance name, name.
virtual function uvm_component create_component ( string  name,
uvm_component  parent )
Creates a component of type T having the provided name and parent.
virtual function uvm_component create_component ( string  name,
uvm_component  parent )
Creates a new component, passing to its constructor the given name and parent.
function uvm_component create_component_by_name ( string  requested_type_name,   
string  parent_inst_path  =  "",
string  name,   
uvm_component  parent    )
Creates and returns a component or object of the requested type, which may be specified by type or by name.
function uvm_component create_component_by_type (
    uvm_object_wrapper  requested_type,   
    string  parent_inst_path  =  "",
    string  name,   
    uvm_component  parent   
)
protected function uvm_sequence_item create_item(
    uvm_object_wrapper  type_var,
    uvm_sequencer_base  l_sequencer,
    string  name
)
Create_item will create and initialize a sequence_item or sequence using the factory.
virtual function uvm_reg_map create_map( string  name,   
uvm_reg_addr_t  base_addr,   
int  unsigned  n_bytes,   
uvm_endianness_e  endian,   
bit  byte_addressing  =  1 )
Create an address map in this block
function uvm_object create_object ( string  requested_type_name,   
string  name  =  "" )
A convenience function for uvm_factory::create_object_by_name, this method calls upon the factory to create a new object whose type corresponds to the preregistered type name, requested_type_name, and instance name, name.
virtual function uvm_object create_object( string  name  =  "" )
Creates an object of type T and returns it as a handle to an uvm_object.
virtual function uvm_object create_object ( string  name  =  "" )
Creates a new object with the optional name.
function uvm_object create_object_by_name ( string  requested_type_name,   
string  parent_inst_path  =  "",
string  name  =  "" )
function uvm_object create_object_by_type ( uvm_object_wrapper  requested_type,   
string  parent_inst_path  =  "",
string  name  =  "" )
The sequence has been allocated.
virtual function uvm_sequence_base current_grabber()
Returns a reference to the sequence that currently has a lock or grab on the sequence.