Personal Details

Name

Avidan Efody

Date of birth

6/6/1975

Martial status

Single

Nationality

Israeli.

Location

Jerusalem

Cell phone

972-(0)50-6541336

Email

avidan_e@yahoo.com

Availability

-

General

· ASIC design and verification engineer with more than seven years of experience.

· Has an excellent knowledge of Specman, SystemVerilog, Verilog & VHDL

· Has an excellent knowledge of testbench design principles and verification methodologies such as eRM and AVM

· Author of www.specman-verification.com

Education

· B.Sc in Electrical Engineering from Tel-Aviv University.

· Areas of specialization: communications and computers hardware.

· Courses: VHDL(1999),Verilog (2001),Specman-e(2001),SystemVerilog(2005)

Workplaces

1/07-

Verification consultant

Verilab, Munich

11/06-12/06

Verification consultant

TI, France (Villeneuve)

9/06-11/06

Verification consultant

Infineon, France (Sophia)

2005-2006

Verification team leader

Siemens, Israel

2005-2006

Specman basic training instructor

Cadence, Israel

2001-2003

ASIC design and verification engineer

Rad Communications, Israel

1999-2001

ASIC design engineer

Powerdsine, Israel

1997-1999

Digital design engineer

IDF, Israel

Sample Projects

SV/AVM/Questa pilot project

The goal of this pilot was to give our client a good estimate of the readiness and maturity of SV verification methodologies and tool support,  and to find out if SV at its current state, was suitable for a complex verification project. This was done by building a complete testbench for an already modified module. As a team member I took part in the following:

• Specification of the requirements from the tool and accompanying methodology
• Specification of required packages such as register packege or stimuli generation package
• Coding of scoreabords, coverage, interrupt handlers and important parts of the generators in SV
• Extensive feedback both to Mentor and to our client on the readiness of SV/AVM and Questa

Ethernet Bridge Verification (Siemens)

In this project, done on behalf of Siemens Israel, I planned and directed the verification of an Ethernet Bridge. I also wrote most of the major parts in the verification environment including generators, drivers, memory models, CPU interface, scoreboards and coverage. The environment, which was built according to eRM principles, included :

• Data path and control path generators
• Memory models for an Sram, a CAM and a QDR
• BFMs for Rgmii, Xgmii, Sssmii, Spi buses
• Packet, control and mac address learning scoreboards

TDMoIP ASIC (Rad Communications)

This ASIC is used in exchange centers in order to send data from legacy TDM equipment over IP networks and vice versa. During its development I took part in the processes listed below:

• Specification of the overall verification environment for the chip
• Writing the infrastructure for this verification environment using Specman e.
• Writing verification environments for specific blocks using Specman
• Specification and implementation of mid-size blocks in Verilog
• Verification of mid-size blocks using Verilog testbenches

ASIC for ringer applications (Powerdsine)

This ASIC is a sine generator controller used in local telephone exchange centers. During its development I took part in the processes listed below:

• Specification and Implemantation of the ASIC using VHDL
• Verification using VHDL testbenches
• Production

Development Environments

Specman, Questa (Modelsim)

Programming languages

e, SystemVerilog, VHDL, C++, TCL/TK, Perl

Work Environments

Windows, Linux

Languages

Level of reading & writing

Level of speaking

Hebrew

Mother tongue

English

Excellent

Excellent

Arabic

Excellent

Very good

French

Very good

Very good

Spanish

good

good

German

good

good