original code

<'
unit env_u {
    clk : in event_port is instance;
    keep bind(clk, external);
    
    cnt : in simple_port of uint (bits:16) is instance;
    keep bind(cnt, external);
        
    !cnt_10s : uint;


    every_clk_tcm() @ clk$ is {
        while(TRUE) {
            if(cnt$ == 10) then {
                cnt_10s+=1;
            };
            wait cycle;
        };
    };
    
    run() is also {
        start every_clk_tcm();
    };
};

extend sys {
    env : env_u is instance;
    keep env.hdl_path() == "~/top";
    keep env.clk.hdl_path() == "clk";
    keep env.cnt.hdl_path() == "cnt";
    
    setup() is also { 
        set_config(run, tick_max, MAX_INT, exit_on, error); 
    }; 
};
    
'>

Sampling-based cpu profile of ncsim -NBASYNC -batch avidan -LICQUE -USELIC IHS:DEFAULT +pmc_dfv_seed=1256797455

• Summary by Phase
• Summary by Category (throughout specman)
• Top Entities by Self + Callees
• Top Entities by Self
• Entity Details

• user methods

  self+	self
  29.91%	20.54%	env_u.every_clk_tcm at line 12 in @every_clock

  
  

• scheduling

  self+	self
  24.55%	24.55%	scheduling

  
  

• temporals

  (#Ticks 400000)
  

  self+	self	#evals	#occs
  11.16%	10.71%	399999	N/A	wait at line 17 in @every_clock

  
  

• long operations

  self+	self
  0.45%	0.45%	long operations

  
  

• list operations

  self+	self
  0.45%	0.45%	list operations

  
  

11	
12	    every_clk_tcm() @ clk$ is {
13	        while(TRUE) {

16	            };
17	            wait cycle;
18		};